Public Release Notes for Altium Designer | Altium Designer User Manual | Documentation

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
This new Altium Designer release continues to deliver new features as well as enhancements to the software’s core technologies, while also addressing many. Release Notes for Altium Designer Version This latest update to Altium Designer continues to deliver new features and enhancements to the software’s.
 
 

 

Release Notes for Altium Designer – Version: | Altium Designer 21 User Manual | Documentation.Public Release Notes for Altium Designer | Altium Designer 22 User Manual | Documentation

 

Setting a component to Fitted via the right-click menu in the Variant Management dialog now functions correctly. New Project dialog no longer prefixes each file with the project name, when the Create Project Folder option is enabled.

Switching a component from Alternate Part to Not Fitted now correctly clears the component parameters. In certain situations, changes made in the Parameter Manager were not applied to all objects, this has been resolved.

Parameters varied in an Alternate Part can now be restored to the original values in the Alternate Part. Alternate Parts no longer produce schematic compiler warnings stating that multiple pins are connected. The order of variants can be changed by clicking and dragging the column header, this new order is retained between edit sessions.

An Out of Resource error no longer occurs when printing a schematic document with an embedded Excel sheet. Layer Stack Manager could be started now if. Net 4. Invalid pointer error fixed in cmplib editor when working with component libraries created in older versions. Fixed error where Objects were accessed after being destroyed when working with the Filter panel. Manually adding a Vault in the Preferences dialog would sometimes causes an invalid handle error, this no no longer occurs.

Model and parameter inheritance in CmpLib files is now correctly handled when opening an older version CmpLib in AD Handling of duplicate UIDs has been strengthened, to ensure that the compiled project correctly synchronizes with the PCB. PCB Release process now continues correctly when non project documents are encountered. Schematic connection highlighting no longer cause incorrect results after deleting wire segments.

The polygon pour order is now used correctly when rebuilding polygons. A problem in the Signal Integrity extension causing an access violation when parsing certain comment fields has been fixed. Objects are now pushed even if the object being moved has a violation.

PCB Polygons now pour correctly when remove necks setting is greater than Electrical clearance. Schematic wire dragging has been greatly improved. Altium Designer now supports file-less editing of vault data. Right-click on Item in vault to edit model, component or managed sheet. Vaults panel right-click menu enhanced to support logical behavior throughout the panel, for example right-click in search results to place, or add to content cart.

BC BC Variants now support the ability to specify a different alternate component. Schematic wire segments can now be individually deleted. Via Shielding tool has been added. Polygon Pour thermal connections now correctly connect to the corners of pads, rather than the center.

PCB Interactive Length Tuning tool and gauge has been improved and patterns can now be modified after placement.

PCB track chamfering has been added. Pressing TAB will cycle through overlapping objects. PCB component placement now uses the Polar Grid to allow automatic rotation to the origin of the grid. Now the used part of the via has been taken into account when calculating the routed length of net. Access violations associated with switching between Sch and SchLib documents and making library edits has been fixed through investigation of crash reports. Commands added to Polygon menus and Polygon Manager dialog.

Loading earlier version designs will change shelved polygons to unpoured state. Libraries panel now supports installing a Vault folder or tree of folders as a library, from which components can be browsed and placed.

Schematic Text Frames no longer display invalid characters when empty. Support for Altium web applications, such as Vault browsing, in Internet Explorer 11 has been improved. Non Altium Designer documents that are stored in a Vault can now be opened in the appropriate editor directly from the Vaults panel.

Additional columns added in the Vaults panel: Item section now includes Note column, and Where-used section now includes State column. Vault web interface has been upgraded, including new Where-Used and Children features and improved browsing capabilities. Schematic wire dragging has been improved when connecting to other wires.

New Junction display and color settings and cursor warning symbol have been added. Browser-based Vault access substantially enhanced to include all of the browsing and searching functionality available in the Vaults panel, as well as a broad range of Vault management features. Schematic Rubber Stamp command now maintains component rotation and mirroring after initial placement.

The PCB Board Outline area is no longer generated in output if the multi-layer or a mechanical layer is enabled. During interactive dragging of a wire end with multiple wires selected, all moving wire ends are displayed. Tiling documents and reopening Altium Designer no longer causes tiled blank space or access violations.

Opening or compiling schematic documents could result in an access violation due to invalid expression references. This has been fixed through investigation of crash reports. Current Polygon editing style is now displayed on the Status bar during interactive polygon editing. Issue where Altium Designer would lose the project’s SVN data, resulting in a project becoming unversioned, has been resolved.

Additions for new Jumper type component, including: automatic net name changes for Jumper pins, and new IsJumperComponent keyword added. Smart PDF from schematic now supports Wingdings font. Schematic objects incorrectly associated with a union while placing and using the insert key has been fixed. Message displayed during update installation reworded to clarify what will happen, now says: Altium Designer must be closed to complete the update process.

Close Altium Designer now? Altium Designer status bar now includes indicators to show state of memory and GDI resource usage. License Management view has been adjusted to show at least three licenses on displays with lower resolution screens. Variants now support parameter inheritance. InViaShielding query keyword added, use this to scope an applicable polygon connect style design rule for shielding copper. A crash when database libraries experience connection problems while placing parts or generating BOM reports has been fixed.

Access violations caused by PCB editing, routing and undo operations have been fixed through the investigation of crash reports. Pads are now generated correctly in Gerber files for flipped Embedded Board Arrays. Variant values are now displayed correctly for Multi-Channel and Complex Hierarchy schematic projects. The Preferences option in the Subversion update repository dialog now works correctly and no longer causes an exception error.

Schematic documents now render non english text correctly when saving between AD10 and AD14 formats. Subversion commit comments now support quotation marks. Subversion commit comments now properly support different language input text. Subversion 1. This also includes support for the new working folder format, as well as updating the built-in Subversion Client to version 1. PCB Polygon repour speed has been significantly improved. Speed increase up to 20x depending on number and complexity of polygons.

PCB footprint primitives are no longer removed from the footprint during interactive routing. PCB Polygon Pour quality has been improved when using hatched style and polygon cutouts. PCB Design Rule dialog will now grey out disabled rules making it easier to distinguish between enabled and disabled rules.

Schematic documents now render text correctly when using non english language system settings. PADS Library importer has been updated to fix specific cases where components were not created. DxDesigner importer has been updated to fix connection issues with off grid objects. PCB Via Stitching has been improved and will now properly use the clearance rule settings.

Schematic directives no longer produce false error reports when single documents are compiled. The Locked attribute is no longer updated when changing the Pad or Via test point settings. Deselecting the Preview top – bottom layer command for a drill table, will no longer cause an Access Violation.

PCB polygon thermal relief calculation causing incorrect DRC violations in some situations has been fixed. The Libraries Panel now remembers the layout when the application is restarted. Smart PDF now displays the correct component parameters when using Variants. BOM generation now supports variant supplier and supplier part number parameters. Variants now support the.

The Schematic “Update From Libraries” command has been updated. The “Preserve Parameter locations” option now works correctly and a new option “Preserve parameter visibility” has been added. Automatic adjustments to track end-points when moving a selected track can now be reliably undone using the Undo feature. The Schematic “Break Wire” command now works with wires that have smallest width setting.

Soldermask now correctly remains as defined for regions and polygons after saving and reloading. Net Antennas with a terminating via are now correctly detected by the DRC. Via Stitching by constrained area no longer causes shorts with polygons on internal layers.

The issue of incorrect From-To lengths has been partially resolved. Length evaluation no longer counts primitives twice when modifying an existing net.

Note: Incorrect evaluation of a complex signal path between points could still occur. The query InFromToClass will return all primitives in the from-to, and will no longer miss track segments. The legend in a generated Drill Drawing now works correctly when using Characters for the. Legend symbols. DXF Exporter now correctly supports slot holes zero line width and donut , and square holes. Debugging embedded project targeting discrete CPU no longer causes a crash on exit.

An issue with the Mixed Simulation engine failing to create the correct netlist has been resolved. There is no longer an Access Violation when printing a schematic containing a large graphic image. IDF Exporter has been fixed to resolve the issue with duplicated board outlines. The Layer Stack Manager dialog now correctly opens in active display space, in accordance with monitor configuration.

An access violation caused by an undo operation in PCB has been fixed through the investigation of a crash report. An access violation associated with importing preference files has been fixed.

Version 6. There is no longer a crash when accessing SchServer. SendMessage through a script. The graphical preview of the schematic part is once again available when accessing the Port Map tab for a Sim Model. Parameters with spaces in their names can now be used indirectly through a part’s Comment field. EAGLE frames have been implemented, the un-named sheets issue addressed, and schematic loading for version 6.

The version number is now correctly checked for the Lattice Diamond toolchain. Vias are no longer removed from existing Via Stitch objects when cancelling the Via Stitch by Area command. CoreGenerator targeting Xilinx devices now correctly generates the FIFO memories for data widths other than multiples of 8. Editing the properties of a component from the SCH Library panel no longer causes the location of that component to change in the panel’s listing of components.

The layer for a placed via can no longer be changed through the PCB List panel. An issue with incorrect library selection in the Libraries panel has been resolved.

The library selected rather than the one under the cursor is now correctly used. An issue whereby the “Flipped on Layer” option was being erroneously set during component placement, has been resolved. The Process Flow after successful synthesis is no longer reset when performing a manual refresh F5. Cortex-M3-based Stellaris Support extension enables programming and debugging for Texas Instruments Stellaris family of microcontrollers.

PCB object transparency levels are now displayed correctly. The slow editing performance when selecting pins in the Schematic Library Editor has been fixed. An access violation with the Silk to Board Region DRC check has been resolved through investigation of a crash report. A “memory error” when opening the Layer Stack Manager dialog has been resolved through investigation of a crash report.

Solder Mask expansion now updates correctly when updating a footprint from a PCB library. BugCrunch An access violation when Board Regions do not have a defined layer stack has been fixed through the investigation of a crash report. Mixed Sim and SIMetrix no longer cause exception errors if models not found or other schematic problems encountered.

Mixed Simulation extension update v1. PCB net name and pad number display issues have been resolved. Schematic editor local language resource files have been updated. Xilinx Spartan 3AN internal flash programming is working correctly now. The “Drill symbol limit exceeded, switching to letter generation” message is now displayed in the Messages Panel instead of a popup dialog.

PCB split planes no longer lose their net assignments when opening and closing the Layer Stack Manager dialog. An issue with DRC Report that affected some boards resulting in additional error counts has been fixed.

The PCB Width rule now correctly calculates the impedance-driven width value. IDF export now associates the correct component footprints when using Integrated Libraries. An access violation when editing union objects has been fixed through investigation of a crash report.

Internal Plane layers are now added correctly to the design when placing snippets or pasting internal plane objects. Step Model cache handling has been improved and crashes associated with “Cannot load 3D model from file” errors have been fixed.

Hyperlynx export now supports 6 digit precision. The Copy Room Formats command now moves objects to the correct layers. An offline version of the Altium Installer is now available for Altium Designer More Information. When starting a Diff Pair route it now picks up the correct track widths.

The initial gathering of traces in the differential pair router has been improved. NanoBoard firmware update is now working correctly. The ‘L’ shortcut key to change PCB routing layers is now working correctly. Film Size checks are now ignored when generating Gerber files and using the “Separate file per layer” Batch Mode option. Fixed memory leak leading to application crash with “runtime error ” while debugging embedded code. A crash that could occur while matching items within the Item Manager has been resolved.

OutJob filenames are now generated correctly when using expressions that contain “. ActiveBOM solutions are now ranked automatically if no ranking exists based on order of existing supplier links contained within schematic components.

ActiveBOM actual pricing is now calculated correctly when item quantity is below the minimum quantity price. Data Management Error occurred when trying to clone a component in the Explorer panel if the folder’s template of the cloned component was deleted.

Schematic A regression caused a crash to occur after placing a Harness Entry if the “Enable Auto Pan” option was enabled.

Data Management A regression caused the software to slow down due to recurring duplicate requests sent to SettingService. BC Error occurred after clicking Enter to commit tracks that have been dragged. Schematic Differential Pairs contained in Harness signals were disconnected in the PCB after updating the design.

BC Port Cross-Reference error message was missing upon the failed attempt to add to the project. BC Objects that were locked using the SCHList panel are not locked and the Locked option is unchecked when the schematic is closed then reopened. BC Image files places from the network folder could not be placed on a schematic.

BC A wire did not return to its initial state if moving a wire vertex was canceled using the Esc key. BC Pin parameters that reference parameters from a database were not displayed correctly. BC An issue caused cross references to adopt signal names rather than port names if a few different ports were connected to the same signal. BC Added an aspect ratio option to the Rectangle mode of the Properties panel.

BC An invalid Clearance Violation appeared after correcting the diameter size for the top layer Pad of a Via. Instancing’ enabled took 60 times longer than with the disabled option. BC Error message populated when attempting to update templates.

BC Platform Text scaling when not using a 4K display in the Properties panel resulted in missing text. BC Error occurred when releasing a component. Printer-friendly version. Found an issue with this document? Contact Us Contact our corporate or local offices directly. We’re sorry to hear the article wasn’t helpful to you. Could you take a moment to tell us why? Connect to Support Center for product questions.

I do not want to leave feedback. When the PCB. EngineX option was disabled in the Advanced Settings dialog, pads were not plated regardless if the ‘Plated’ option in the Pad mode of the Properties panel and the PCB List panel was checked or unchecked.

PCB: The Undo command does not always function correctly after moving components if the Component re-route option is enabled in the Interactive Routing preferences.

Some bitmaps were truncated in the generated PDF document. The Smart PDF output did not include embedded graphics. When the revision of the managed sheet is replaced, the Annotation file becomes invalid.

Custom locations of cross reference parameters are reset to defaults after saving and reloading the schematic document. The page scaling in the Print dialog was displayed incorrectly. Superscripts located in multi-channels displayed the previous designator rather than the logical designator.

The Physical checkbox in the Component Designator dialog will maintain its enabled or disabled state until the software is closed. Values of alternate part parameters were missing for a design variant that is not selected. Error appeared when exporting a Parasolid file when the ‘Export All Copper’ option was enabled.

The rotation column did not respect the comma and period separator change in the Pick and Place Setup dialog. No Net split planes were not detected in the Unrouted Net rule. Unnecessary controls were selected when using the Tab keyboard shortcut in some object properties panels BC Pads that were set to ‘rectangular’ and contained a hole size equal to its length were not displayed in the Drill Table.

Hatched polygon pour did not obey polygon cutouts near obstacles, which caused violations to occur. The project repository type was incorrectly recognized and the Make Available Online operation failed. The “- Snapshot from ” suffixes are now added to generated design snapshots to distinguish them from live WIP designs. A DC-shortened net error occurred for net tie components with through-hole pads in the Ansys Exporter.

Measurement information is now provided in the Output Expressions region of the Simulation Dashboard panel. A model file error was displayed in the Simulation Dashboard panel for an IC component model when the Initial Voltage parameter is set. The page tiling and scaling in the Print Preview dialog was incorrect if the paper size is smaller than the schematic sheet size with the scale set to 1 BC Some footprints that were generated from the database library could not be found in the Footprint Manager.

Pin designators were far from pad numbers at some custom pin configurations when pins are mapped to multiple pads. The print preview only displayed the active document instead of all schematic documents in the project.

Some graphical images were stretched in the software and Web Viewer. A list of text copied from Excel was pasted as bitmaps rather than net labels after enabling the ‘Paste as Net Labels’ option in the Smart Paste dialog. Pullbacks were not shown and an incorrect number of split planes were created on a specific PCB design.

Selection made with the Enter or spacebar keys caused data from the Properties panel of an object to be deleted. A delay in the Properties panel setup results in an invalid multi-line width text box for Interactive Routing.

Layer Drawing Order settings were not saved to preferences files. An error occurred when opening the composite drawing output for some PCB documents in an Outjob. Some objects are missing in an exported PDF file. After modifying more than one footprint in a component, update of components using the same footprints was incorrect. A error occurred when reverting a revision of a project document through the Storage Manager panel if this document has been renamed.

The Comments panel loaded comments endlessly after running comment placement if automatic signing in to AltiumLive is disabled. The private server license did not release the license when the software was closed. Implemented a “Schematic was done in newer version” warning to notify users that new functionalities were introduced between the version of Altium Designer that was used to create the schematic and the version used to open the schematic document.

The Show Net Color Override command does not work correctly when using F5 or when invoking the command from the View menu. A background compilation error occurred after opening a specific project, and a crash occurred after performing some operations on its schematics. The Find Text – Jump dialog can now be closed by using the Esc key. Added ability to show all Parameters in the Component mode of the Properties panel. Two digital numbers surrounded by parentheses were interpreted as a number rather than a string in the concatenation of parameters.

Added ability to disable the use of paste mask to the Paste Mask Expansion design rule, the Pad mode of the Properties panel, and the Pad Template Editor. Document could not be saved after reconnecting to a VPN. Software performance degradation during layer cycling when a routing via needs to push too many objects.

When placing non-inverted graphics, some QR codes are placed incorrectly with an extra filled rectangle. Location of the “. Added the Room mode of the Properties panel. When a polygon cutout is indirectly built to a net tie footprint, using the ‘Verify Shorting Copper’ option of the DRC generates a net tie verification failure.

Hatched polygon pours do not respect polygon pour cutout boundaries. Improvements for interactive routing with SMT rules include rules are now applied when using ‘Any Angle’, routing does not fail if all allowed exits are blocked, and routing is more stable after exiting an SMD.

If a Line primitive is not on any of the assembly layers used in a component, the Variant ‘Drawing Style’ is not applied. When generating a Gerber report with a design view that is mirrored, the layer description and layer extension do not match. When a project is released, the. Performance degradation occurred when opening a PCB if there is an issue with the Collaboration Service connection.

An incorrect icon was used for the ‘Comments’ command in the right-click menu of the schematic and PCB editors and on the Schematic Standard toolbar. A pinned or docked state of a panel was not saved after software relaunch. Renaming a master branch in an external Git repository resulted in absence of project data after making it available on a server. After auto-updating or refreshing, the project still displays as ‘Up to date’ and there are no error messages.

The ability to sweep more than two parameters in the Parametric Sweep has been added. The X,Y scale settings for plots are now kept during the simulation process for opened and saved. Voltage on an independent voltage source is now supported as an output variable in DC and Transient Analysis. Power on functional voltage and current sources is now supported as an output variable in DC and Transient Analysis. Voltage on the current switch is now supported as an output variable in DC and Transient Analysis.

Current for an independent current source model is now supported as an output variable in DC and Transient Analysis. Conductance on a current switch is now supported as an output variable in DC and Transient Analysis.

Voltage on a voltage switch is now supported as an output variable in DC and Transient Analysis. Conductance on a voltage switch is now supported as an output variable in DC and Transient Analysis. Bottom side components were removed from a specific design after resaving the layer stack in the Layer Stack Manager.

The ‘Undo’ command did not function after a footprint was added to a schematic document from SamacSys. An access violation occurred when selecting print preview for an Export Comments report in an OutJob file. On the Drawings tab of the Print dialog, the Parameter Sets option cannot be disabled. When quotes were used to concatenate parameters, the concatenation was interpreted incorrectly in the BOM for components located in the project hierarchy.

The tooltip was not displayed correctly when a NoERC was placed over crossed wires. Multiple differential pair rules were created targeting individual nets instead of a single rule. Columns are now displayed in alphabetical order in the Parameter Table Editor dialog.

There are no component parameters in the generated PDF if ‘Schematic Prints’ is not set as the first to be generated. Drill symbols did not appear in the PCB document for embedded board arrays. Cavities are missing in 3D mode. Rooms could not be selected if PCB primitives overlapped the rooms. One endpoint of the Standard Dimension object could not be moved when placed between two Line objects.

Only the Length rule was displayed in the Properties panel when different values for the Length and Matched Length rules were selected. Surface mount pads appeared rectangular when the “Rounded Rectangle” shape was used and viewed in 3D mode. Creating a new rectangle using the ‘Place Rectangle’ command with the mouse caused changes in dimensions.

When there was a not-fitted component on the top side, the mark of this component was shown on the bottom side in the PCB printout. The via stack type changed to Simple mode after the editing of middle layer parameters is undone. Pad and via previews were displayed incorrectly.

Keepout objects that were generated as copper caused a short-circuit to occur between polygon and track objects when exported from Ansys EDB.

Rectangle size was decreased upon each copy and paste operation if the track width was less than 10mil. Mask options were incorrectly applied on the Board Realistic View. Software crashed when adding a Draftsman document to a newly created project when signed into the Nexus Server. Component body and designator objects were reenabled after using the Import Changes from PCB command.

Cross has been added to the Variants Display field. Board outlines and holes were displayed underneath the component after the file was exported to PDF. Draftsman Board Realistic View cropped any connectors that were on the edge of the board.

The Layer Stack Stable settings would return to default when a new Draftsman document was created from a template. Hexagon and flag shapes have been added to the Callout object to prevent conflicts with existing mechanical drawing standards. The Refresh button did not function after modifying a sheet template. After a DRC is created in a separate window, the system quickly and constantly switches from one window to the other. Making Projects Available Online with source files outside of a Project folder is now prevented.

It was not possible to commit a new project into a SVN repository through version control. Centroids Casm. When exporting IPC components and pads that are located on the bottom layer, they are exported with the wrong orientation. ECO changes a dot to a comma with the concatenation of parameters if Windows regional settings are set to German where a decimal point is set to a comma.

The parameter is not rotated after selecting it on the schematic then pressing the Spacebar. Regression caused leading spaces to not be trimmed in certain projects. Slow performance when panning while actively placing an object. Added a warning about the presence of shelved polygons before generating outputs.

Plane region TH pads have no thermal spokes. In the Component Rule Check, Keepout primitives in footprints are treated as unconnected with ‘Unconnected Copper’ warnings. Added an option in the Advanced Settings dialog that allows disabling of the auto-renaming of polygons. There was a performance delay when moving several components with parameters when the Properties panel is open. Added the PCB. Polygon repouring did not work correctly in hatched polygons in rigid-flex designs.

The Board Outline Clearance design rule option was not respected in certain solder mask and paste mask layers. Solder mask and paste mask layers were not present in gerber files when rigid flex was used. Only unique solder masks and paste masks will be generated on separate layers, while standard solder masks and paste masks will be generated on the same. After changing the diameter of a via, the clearance violation is not detected with online or batch DRC.

Paste and Solder Mask Expansions for regions, fills, and pads are not displayed for primitives placed on outer layers of flex thinner stacks. The Draftsman – Defaults and Properties panel options are different for Callouts. Layer settings, colors and grids were not properly transferred for newly created Footprints when using a Template BC If a custom filename was used in an outjob file, the filename did not always follow the filename settings.

The error “Server did not recognize the value of HTTP Header” was displayed after clicking “Use local file name” if the project was renamed. It was not possible to select a BOM template from a folder in the Reports Manager when connected to a server. Added a ‘Remove from project’ decision dialog that allows you to choose how to remove a document. Dynamic Compilation resulted in a loss of connectivity where Pins were incorrectly removed from the Net.

Dynamic Compilation displayed incorrect violation of “Unconnected Objects in Net” when objects were connected. Symbol parameter locations are reset when one of the parameters is getting hidden BC Changes made on the Schematic – Grids page of the Preferences dialog are not applied to open schematics. Grid was misaligned when metric units were used. Cursor was shifted from the snap point after a component was double-clicked in the Components panel.

Additional options added to filter data displayed on the embedded board array. BC ; BC When importing files into Ansys, some components resistors, inductors, capacitors are not defined correctly.

Restored the ability to change the coverlay color in the View Configuration panel. Some components cannot be selected and moved.

An output job that had a fabrication outputs test point report set to IPC-DA report format with an output file that included periods and a PCB document with an embedded board array resulted in a generated file missing the “. The UnRouted Net Constraint flags connections made with fills and solid regions of copper if the ‘Check for incomplete connections’ option is checked, however, the PCB panel states 0 unrouted nets.

When running a Design Rule Check for the first time, the parallel segment rule was not highlighted or zoomed in on. When opening a multichannel PCB, the bounding box of logical designators extends to the size of the physical designators. When opening an. Special String for a Parameter displayed its value rather than the name.

Slow performance when switching to single-layer mode when the PCB panel was opened in Nets mode. Solder mask expansions are not displayed for multi-layer regions and cutouts.

Added an option to the PCB Editor – Interactive Routing page of the Preferences dialog that allows you to specify the number of pins when the ‘Move component with relevant routing’ option is enabled. Optimization for unnecessary postprocessing when modified primitives cannot affect DRC. Route Tool Path displays incorrect dimensions. Improved the display of parameter priorities. It was not possible to add a local Draftsman template when signed in to Altium When the designator of a component on the PCB is changed, the component designator and component body resets to their defaults for the component in the Board Assembly View.

The Component Display Properties could not be saved as a template. If Callouts that are not pointing to a source are being used in Draftsman documents, the Print option and export to PDF fail.

Tented vias were hidden when the SolderMaskExpansion design rule was applied before a document was updated. Added the ability to select multiple components in a Board Assembly View. Added the ‘Override Color’ option for a Board Fabrication View that allows you to set the default color for all layers. When a panel header was clicked, all other panels that are docked to that panel were initialized.

Project Releaser caused an abnormally long wait time if no modified files were present during VCS check. The ‘. Added additional fields to the Add Output Expression dialog to provide wide wave to plot compabilitbility. Repeated font setting actions were needed to apply properties for multiple text objects.

The justification of net labels printed to a PDF with Physical Structure is incorrect if the justification is set to Right. Smart Edit for a pin designator in a schematic library document does not add the numeric value when using the formula ‘!

Received error during netlist generation. The position of the string over the not-fitted component’s graphics was not aligned to the center of symbol.

Project templates containing schematic sheets in the subfolder resulted in invalid messages about duplicate designators and several sheets with the same name. Special strings in schematic don’t reflect project options parameters BC Some schematic files displayed a blanket as diagonal lines. The visibility of the “Comment” Name was not saved after applying changes in the Schematic – Defaults page of the Preferences dialog.

It was not possible to edit a text object editing if it was selected by the mouse’s right-left selection motion. Text wrapping for a note does not work properly.

It was not possible to select local schematic templates when the layout customizations were already configured. Missing BOM variants for multi-part components if the variants were on different sheets of the hierarchical design. Received an error during ECO if pad designators contained dashes. The Board Information Report was not taking hidden nets into account for the ‘Routing completion’ information.

Design Outputs did not export the rotation of pads from the Solder Mask layer for a package correctly. Snapping does not work properly when dragging vias or tracks if the corresponding snap options are enabled in the Properties panel. Snapping to arc centers did not function properly. Snap points were displayed even though they were disabled in the Guide Manager region of the Properties panel. Added the ability to lock 3D Board Regions.

An issue caused text placed on a polygon to not be selectable after the polygon was moved or flipped.

 
 

Public Release Notes for Altium Designer | Altium Designer 21 User Manual | Documentation

 
 
Pad designators are now displayed rather than the Pin designator in the case of unsymmetrical pin to pad mapping. An option has been added to suppress output of component parameters when sesigner to PDF.